ASIC/FPGA Design Verification Engineer (contract)
Title: ASIC/FPGA Design Verification Engineer with UVM Experience
Create UVM simulation plan from design specification. Create or modify UVC, Score Board, Monitor, and test cases. Verify until functional coverage and code coverage meet project threshold. Document results.
Create UVM simulation plan from design specification. Create or modify UVC, Score Board, Monitor, and test cases. Verify until functional coverage and code coverage meet project threshold. Document results.
-
Seniority level
Entry level -
Employment type
Contract -
Job function
Engineering and Information Technology -
Industries
Aviation & Aerospace
Referrals increase your chances of interviewing at Boeing by 2x
See who you knowGet notified about new Design Verification Engineer jobs in El Segundo, CA.
Sign in to create job alertSimilar Searches
Looking for a job?
Visit the Career Advice Hub to see tips on interviewing and resume writing.
View Career Advice Hub